1. Field of the Invention
Generally, the present disclosure relates to microstructures, such as advanced integrated circuits, and, more particularly, to conductive structures, such as copper-based metallization layers, comprising metal lines and vias.
2. Description of the Related Art
In the fabrication of modem microstructures, such as integrated circuits, there is a continuous drive to steadily reduce the feature sizes of microstructure elements, thereby enhancing the functionality of these structures. For instance, in modern integrated circuits, minimum feature sizes, such as the channel length of field effect transistors, have reached the deep sub-micron range, thereby increasing performance of these circuits in terms of speed and/or power consumption and/or diversity of functions. As the size of individual circuit elements is reduced with every new circuit generation, thereby improving, for example, the switching speed of the transistor elements, the available floor space for interconnect lines electrically connecting the individual circuit elements is also decreased. Consequently, the dimensions of these interconnect lines are also reduced to compensate for a reduced amount of available floor space and for an increased number of circuit elements provided per unit die area as typically the number of interconnections required increases more rapidly than the number of circuit elements. Thus, usually a plurality of stacked “wiring” layers, also referred to as metallization layers, is provided, wherein individual metal lines embedded in a dielectric material of one metallization layer are connected to individual metal lines of an overlying or underlying metallization layer by so-called vias. Despite the provision of a plurality of metallization layers, reduced dimensions of the interconnect lines are necessary to comply with the enormous complexity of, for instance modern CPUs, memory chips, ASICs (application specific ICs) and the like.
Advanced integrated circuits, including transistor elements having a critical dimension of 0.05 μm and even less, may, therefore, typically be operated at significantly increased current densities of up to several kA per cm2 in the individual interconnect structures, despite the provision of a relatively large number of metallization layers, owing to the significant number of circuit elements per unit area. Consequently, well-established materials, such as aluminum, are being replaced by copper and copper alloys, i.e., materials with significantly lower electrical resistivity and improved resistance to electromigration even at considerably higher current densities, compared to aluminum. The introduction of copper into the fabrication of microstructures and integrated circuits comes along with a plurality of severe problems residing in copper's characteristic to readily diffuse in silicon dioxide and a plurality of low-k dielectric materials, which are typically used in combination with copper in order to reduce the parasitic capacitance within complex metallization layers.
Another characteristic of copper significantly distinguishing it from aluminum is the fact that copper may not be readily deposited in larger amounts by chemical and physical vapor deposition techniques and it does not form volatile etch byproducts when exposed to currently established etch processes, thereby requiring a process strategy that is commonly referred to as the damascene or inlaid technique. In the damascene process, first a dielectric layer is formed, which is then patterned to include trenches and/or vias which are subsequently filled with copper, wherein, prior to filling in the copper, a conductive barrier layer is formed on sidewalls of the trenches and via openings. The deposition of the bulk copper material into the trenches and via openings is usually accomplished by wet chemical deposition processes, such as electroplating and electroless plating, thereby requiring the reliable filling of vias with an aspect ratio of 5 and more with a diameter of 0.3 μm or even less in combination with trenches having a width ranging from 0.1 μm to several μm.
In addition, to achieve high production yield and superior reliability of the metallization system, it is also important to accomplish these goals on the basis of a high overall throughput of the manufacturing process under consideration. For instance, the so-called dual damascene process is frequently used, in which a via opening and a corresponding trench are filled in a common deposition sequence, thereby providing superior process efficiency.
In the damascene technique or inlaid technique, typically, the patterning of the via openings and the trenches may require sophisticated lithography techniques since the shrinkage of critical dimensions in the device layer, i.e., for transistors and other semiconductor circuit elements, may also require a corresponding adaptation of the critical dimensions of the vias and metal lines to be formed in the metallization system. In some well-established process techniques, a patterning regime may be used, which may commonly be referred to as “via first-trench last” approach, in which at least a portion of a via opening may be formed first on the basis of a specific etch mask and thereafter a corresponding trench mask may be provided in order to form a corresponding trench in the upper portion of the dielectric material, wherein, depending on the overall process strategy, during the trench etch process, the remaining portion of the via opening may also be completed, while, in other cases, the via opening may be provided such that it extends down to a bottom etch stop layer, which may then be opened after or upon completing the trench etch process.
With reference to FIG. 1, a typical process flow for forming a complex metallization system will now be described in more detail. FIG. 1 schematically illustrates a cross-sectional view of a semiconductor device 100 comprising a substrate 101, above which is formed a metallization system 150. The metallization system 150 typically provides the required electrical connections between a plurality of circuit elements 110, which are formed in and above a semiconductor layer 102. For example, the semiconductor layer 102 may represent any appropriate semiconductor material, such as a silicon material, a silicon/germanium material and the like, in order to form therein any complex circuit elements, such as field effect transistors, bipolar transistors, resistors, capacitors and the like. It should be appreciated that the semiconductor layer 102 in combination with the substrate 101 may represent a bulk configuration in which the semiconductor material of the layer 102 is directly in contact with a crystalline substrate material, while, in other cases (not shown), a buried insulating material, such as a silicon dioxide material and the like, may be provided so as to form a silicon-on-insulator (SOI) configuration. As discussed above, the circuit elements 110 may have critical dimensions, such as a gate length of a field effect transistor, of 50 nm and less, if highly complex applications are considered. Typically, the semiconductor-based circuit elements 110 are embedded in an appropriate dielectric material or material system 121 of a contact level 120, which in turn comprises appropriate contact elements 122, i.e., highly conductive vertical connections, which finally connect the circuit elements 110 with the metallization system 150.
As explained above, the metallization system 150 typically comprises a plurality of metallization layers, depending on the overall complexity of the device 100. For convenience, a first metallization layer 130 and a second metallization layer 140 are illustrated in FIG. 1. The metallization layer 130 comprises a dielectric material 131, such as a low-k dielectric material, a ULK material and the like. Furthermore, a metal line or region 132 is formed in the dielectric material 131 and typically comprises a highly conductive core metal 132A, such as copper, copper alloys and the like, in combination with an appropriate barrier material or material system 132B. For example, tantalum, tantalum nitride and the like are well-established barrier materials for copper-based metallization systems.
Similarly, the metallization layer 140 comprises an appropriate dielectric material 141, such as a low-k dielectric material, a ULK material and the like, in which are formed metal regions 142, such as metal lines 142L in combination with appropriate vertical contacts, which are referred to herein as vias 142V. Also in this case, a highly conductive core metal 142A in combination with a barrier material or material system 142B is typically applied. Furthermore, as a part of the metallization layer 130 or the metallization layer 140, an etch stop layer 135 is typically provided, which may be efficiently used as an etch control mechanism upon forming the vias 142V, as will be explained later on in more detail.
As discussed above, in highly complex semiconductor devices, the overall performance is typically significantly affected by the propagation delay caused by the metallization system 150, which is addressed by using highly conductive metals in combination with dielectric materials of reduced permittivity. In this manner, the parasitic capacitance between the metal lines 142L and any lower-lying metal lines, such as the metal line 132, are thus significantly influenced by the dielectric characteristics of the materials 141 and 135. Since the layer 135 has to provide sufficient etch stop capabilities, possibly in combination with cap layer capabilities for providing superior electromigration behavior of the metal line 132, it is very difficult to find appropriate materials with reduced dielectric constant, while also a significant reduction in overall thickness is less than desirable, in particular in view of the etch control capabilities required for patterning the dielectric material 141. For this reason, frequently, the dielectric constant of the material 141 is further reduced, for instance by incorporating ULK materials, which, however, may exhibit a significantly reduced mechanical and chemical stability.
The semiconductor device 100 as illustrated in FIG. 1 may be formed on the basis of the following processes. The circuit elements 110 in and above the semiconductor material 102 are formed on the basis of any appropriate process technique, including complex lithography techniques, etch techniques, deposition techniques, implantation processes, anneal processes and the like, in order to obtain the circuit elements 110 having the desired critical dimensions. After any high temperature processes, the contact level 120 is typically provided, for instance, by depositing the dielectric material or materials 121, planarizing the same and performing a complex patterning process for forming openings therein, which are subsequently filled with an appropriate conductive material, such as tungsten and the like. Thereafter, any excess material is removed and the metallization system 150 may be formed, for instance, by depositing an appropriate dielectric material and patterning the same. A corresponding manufacturing flow will now be described for the metallization layer 140, wherein it should be appreciated that a similar process sequence may also be applied to any lower-lying metallization layer, such as the metallization layer 130, and also to any further metallization layer that may possibly be required above the metallization layer 140.
After forming the metal lines 132, the etch stop layer 135 may be formed, for instance, by appropriate deposition techniques including plasma enhanced chemical vapor deposition (CVD) and the like, wherein, typically, at least one layer including a silicon nitride-based material is used due to its very efficient copper diffusion blocking effect and the etch stop capability with respect to plasma assisted etch recipes, which are typically used for patterning the plurality of low-k and ULK materials. Typically, silicon nitride-based dielectric materials may have a dielectric constant of 4.0 and higher, which may, therefore, unduly increase parasitic capacitance 144. Thereafter, the dielectric material 141 is formed, for instance by spin-on techniques, CVD and the like, possibly in combination with additional treatments in order to adjust the finally desired dielectric constant. For example, frequently, the material 141 is provided in the form of a porous material in order to further reduce the dielectric constant. In many conventional approaches, the dielectric constant of the material 141 is reduced in order to compensate or even over-compensate for the contribution of the layer 135 to the total parasitic capacitance 144. After the deposition of the material 141 and adjusting its material characteristics, if required, for instance by radiation treatment and the like, a complex patterning sequence is applied in which, typically, an appropriate etch mask is provided, which may be obtained on the basis of appropriate lithography masks, which thus determine the lateral position and size and shape of the metal features 142. In the “via first-trench last” approach, a first etch mask is applied and used for patterning the dielectric material 141, at least to a certain depth, followed by a further patterning process in which an etch mask for defining the size and position of trenches is produced. During the patterning of respective via openings or during a final phase of a common etch process for increasing the depth of the previously formed via and the trenches, the etch stop layer 135 is used as an efficient etch control mechanism in which the high etch resistivity enables appropriate over-etch times so as to reliably form the via openings across the entire die regions and also across the entire substrate 101. Thereafter, the etch stop layer 135 is opened in a dedicated etch step so as to connect to the metal line 132. Thereafter, the barrier material 142B followed by the highly conductive core metal 142A are deposited by using well-established process techniques, followed by the removal of any excess material, for instance by chemical mechanical polishing or planarization (CMP) and the like.
As indicated above, upon further reducing the overall device dimensions, the parasitic capacitance 144 may be increased, for instance, by reducing the distance between the metal lines 142L and 132, which is typically compensated for by further reducing the dielectric constant of the material 141, while a pronounced reduction of the dielectric characteristics of the etch stop layer 135 is typically limited due to the required etch stop capabilities and due to the fact that the thickness of the layer 135 may not be arbitrarily reduced. It has been observed, however, that a further reduction of the dielectric constant of the material 141 may result in significant instabilities of the metallization system 150, while also increased etch damage may occur upon patterning the material 141, which may result in a compensation or even an increase of the finally obtained dielectric constant. That is, upon exposure of the material 141 to the reactive etch atmosphere, the surface characteristics may significantly change such that polar molecules such as OH-groups and the like may preferably adhere to the exposed surface areas, thereby locally significantly increasing the dielectric constant, which in turn may negatively affect the resulting parasitic capacitance 144.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.